High Performance Packet Processing in the NFV World

Network transformation is taking off like a rocket … with the SDN, NFV, and network virtualization market accounting for nearly $10 Billion (USD) in 2015, according to SNS Research.(1) This momentum will take front stage this week at Mobile World Congress (MWC) 2015, including dozens of solutions and demos that spotlight Intel technology.

New Ways to Speed up Packet Processing

Packet processing workloads are continuously evolving and becoming more complex, as seen by progressing SDN/Network-overlay standards and signature-based DPI, just to name a few examples. One requires highly flexible software and silicon ingredients to deliver cost-effective solutions to cater to these workloads. NFV solutions are all judged on how fast they can move packets on virtualized, general-purpose hardware. This is why the Data Plane Development Kit (DPDK) is seen as a critical capability, delivering packet processing performance improvements in the range of 25 to 50 times( 2, 3) on Intel® processors.

Building upon the DPDK, Intel will demonstrate at MWC how equipment manufacturers can boost performance further while making NFV more reliable. One way is to greatly reduce cache trashing by pinning L3 cache memory to high-priority applications using Intel Cache Allocation Technology. Another is to use a DPDK-based pipeline to process packets instead of distributing the load across multiples cores, which can result in bottlenecks if the flows cannot be uniformly distributed.

Intel Cache Allocation Technology

It’s no secret that virtualization inherently introduces overheads that lead to some level of application performance degradation compared to a non-virtualized environment. Most are aware of the more obvious speed bumps, like virtual machine (VM) enters/exits and memory address translations.

A lesser known performance degrader is caused by various VMs competing for the same cache space, called cache contention. When the hypervisor switches context to a VM that is a cache hog, cache entries for the other VMs get evicted, only to be reloaded when those VMs start up again. This can result in an endless cycle of cache reloads that can cut performance in half, as shown in the figure. (2, 3)

DPDK MWC Blog Graphic.jpg

On the left side, the guest VM implementing a three-stage packet processing pipeline (classify, L3 forward, and traffic shaper) has the L3 cache to itself, so it can forward packets at 11 Mpps. The middle pane introduces an aggressor VM that consumes more than half the cache, and the throughput of the guest VM drops to 4 Mpps. The right side implements Intel Cache Allocation Technology, which pins the majority of the cache to the guest VM, thus restoring the packet forwarding throughput to 11 Mpps. (2, 3)

IP Pipeline Using DPDK

There are two common models for processing packets on multi-core platforms:

  • Run-to-completion: A distributor divides incoming traffic flows among multiple processor cores, each processing their assigned flows to completion.
  • Pipeline: All traffic is processed by a pipeline constructed of several processor cores, each performing a different packet processing function in series.

At MWC 2015, Intel will have a live demonstration of high-performance NFV running on industry standard high volume server, where copies of packet processing pipelines are implemented in multiple VMs, and the performance of these VMs is governed using state-of-the-art Cache Monitoring and Allocation Technologies.

Want to know more? Get more information on Intel in Packet Processing.

Are you at MWC 2015?

Check out the high-performance NFV demo at the Intel Booth and see the new Intel technologies developed to drive even higher levels of performance in SDN and NFV! Visit us at MWC 2015 - App Planet, hall 8.1, stand #8.1E41.

1 Source: PR Newswire, “The SDN, NFV & Network Virtualization Bible: 2015 - 2020 - Opportunities, Challenges, Strategies & Forecasts.” Nov 27, 2014, http://www.prnewswire.com/news-releases/the-sdn-nfv--network-virtualization-bible-2015--2020--opportunities-challenges-strategies--forecasts-300002078.html.

2 Performance estimates are based on L2/L3 packet forwarding measurements.

3 Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel® products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations.