Itanium Poulson Update – Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips!

Intel is using this week’s Hotchips  conference to disclose additional new information about its next generation  Itanium chip, codenamed Poulson.

The initial Poulson details (8 cores, 3.1 Billion  transistor, 32nm process) were disclosed at the International  Solid State Circuit Conference earlier this year.  While Itanium customers are always interested  in coming attractions, it’s also worthwhile for Intel Xeon Server customers to  also keep an eye on the evolution of Itanium, as many features originally  introduced on Itanium  often waterfall  down to subsequent generations of Xeon CPU chips.  Remember that Poulson, like the current Intel  Itanium 9300 processor shares many common platform ingredients with Xeon,  including the Intel QuickPath and Scalable Memory Interconnects, the Intel 7500  Scalable Memory Buffer and DDR3, and the Intel 7500 Chipset.

So, what’s new?  There  are three key feature areas.  The first  is Intel Instruction Reply Technology, which is a major RAS enhancement.  This is the first Intel processor with  Instruction Replay RAS capability, and it utilizes a new pipeline architecture  to expand error detection in order to capture transient errors in execution. Upon  error detection, instructions can then be re-executed from the instruction  buffer queue to automatically recover from severe errors to improve resiliency.

The same instruction buffer capability also enables the  second new feature, an improved Hyper-Threading Technology. It supports performance  enhancement with Dual Domain Multithreading support, which enables independent front and  backend pipeline execution to improve multi-thread efficiency. As EPIC  architecture is already known for its highly parallel nature, this enhancement  will help take Poulson’s overall parallelism to the next level.

Lastly, Poulson is adding new instructions in four key  areas.  First there are new Integer  operations (mpy4, mpyshl4, clz). In support of the higher parallelism and multithreading  capabilities, there is expanded Data Access Hints (mov dahr), Expanded Software  Prefetch (ifetch.count) and Thread Control (hint@priority). These new  instructions lay the foundation for the Itanium architecture to grow with  future needs.

As you can see, most of these features are designed to take  full advantage of the 8 core, 12-wide issue architecture by enabling the  maximum amount of parallel execution. Poulson is on track for 2012 delivery (if  you attended HP Discover you may have had a chance to actually see an active Poulson  system!)  and the follow-on future  Kittson processor is under development.

If you’d like to learn more details check out the full Hotchips presentation.