Meet the one and only Ajay Bhatt and other Intel Technology Rock Stars and learn more about what it took to create PCI, PCIe and USB initiatives

Meet the Rock Stars of PCI, PCI Express and USB Initiatives at IDF.

The real Ajay Bhatt and other Intel Rock Stars will be on hand to take your questions about PCIe and USB.  You might even get him to sign an Ajay Bhatt t-shirt if you ask a question that’s not too hard for him to answer!

  • This event is on Tuesday Sept 22nd at 6pm in room 2004, level 2.

  • For the real scoop on what’s going on in PCIe today

    • consider attending the following sessions on Thursday, Sept 24th in room 2003 starting at 11.10am.

11.10-Noon: TCIS006: PCI Express* 3.0 Technology: Device Architecture optimizations on Intel Platforms

This session is for developers with advanced knowledge of PCI Express* Technology and related usage models. This session will help developers comprehend platform implementation challenges and what is needed to build the ecosystem for successful product deployment.

Topics include:

  • Overview of PCI Express* (PCIe*) 2.1 and 3.0 technology protocol extensions as well as the power/performance benefits and applicability across various market segments
  • Implementation considerations for a selected set of PCIe Technology protocol extensions aimed at Intel based platforms
  • Software development required for these features.

1.40-2.30pm: TCIS007: PCI Express* 3.0 Technology: PHY Implementation Considerations on Intel Platforms

This session is intended for developers with advanced knowledge of PCI Express* Technology.

This session will help developers appreciate, understand, and address implementation challenges related to the encoding scheme.

Topics include:

  • An overview of Intel’s analysis of the logical layer enhancements required for the PCI Express* 3.0 technology operating at 8.0 GT/s
  • Implementation challenges and considerations for Intel based platforms.

2.40-3.30pm: TCIS008: PCI Express* 3.0 Technology: Electrical Requirements for Designing ASICs on Intel Platforms

This session will focus on the electrical and mechanical elements of designing PCIe with topics to include:

  • Overview of silicon and motherboard/add-in card design features required to support typical PCI Express* Technology one connector and two connector topologies at 8.0 GT/s
  • Analysis of studies for deeper understanding of transmit and receive equalization schemes, measurement, and testing
  • Process for determining form factor specific electrical requirements, PCB design guidelines, and add-in card and motherboard test methodologies.

3.40-4.10pm: TCIQ002: Q&A and panel on PCI Express

Get any lingering questions you have on PCIe at this open session where no PCIe question will go un-answered!