On the Ground at SC14: The Intel HPC Developer Conference

SC14 is officially under way, however the Intel team got in on the action a bit early and I’m not just talking about the set up for our massive booth (1315 – stop by to see the collaboration hub, theater talks and end-user demos). Brent Gorda, GM of the High Performance Data Division, gave a presentation at HP-Cast on Friday on the Intel Lustre roadmap. A number of other Intel staffers gave presentations ranging from big data to fabrics to exascale computing, as well as a session the future of the Intel technical computing portfolio. The Intel team also delivered an all-day workshop on OpenMP on the opening day of SC14.

On Sunday, Intel brought together more than 350 members of the community for an HPC Developer Conference at the Marriott Hotel to discuss key topics including high fidelity visualization, parallel programming techniques/software development tools, hardware and system architecture, and Intel Xeon Phi coprocessor programming.

The HPD Developer Conference kicked off with a keynote from Intel’s Bill Magro discussing the evolution of HPC – helping users gain insight and accelerate innovation – and where he thinks the industry is headed:

Beyond what we think of as traditional research supercomputing (weather modeling, genome research, etc.) there is a world of vertical enterprise segments that can also see massive benefits from HPC. Bill used the manufacturing industry as an example – SMBs of 500 or less employees could see huge benefits from digital manufacturing with HPC but need to get beyond cost (hardware/apps/staff training) and perceived risk (no physical testing is a scary prospect). This might be a perfect use case for HPC in the cloud – pay as you go would lessen the barriers to entry, and as the use case is proved and need grows, users can move to a more traditional HPC system.

Another key theme for the DevCon was code modernization. To truly take advantage of coprocessors, apps need to be parallelized. Intel is working with the industry via more than 40 Intel Parallel Computing Centers around the world to increase parallelism and scalability through optimizations that leverage cores, caches, threads, and vector capabilities of microprocessors and coprocessors. The IPCCs are working in a number of areas to optimize code for Xeon Phi including aerospace, climate/weather modeling, life sciences, molecular dynamics and manufacturing. Intel also recently launched a catalog of more than 100 applications and solutions available for the Intel Xeon Phi coprocessor.

Over in the Programming for Xeon Phi Coprocessor track, Professor Hiroshi Nakashima from Kyoto University gave a presentation on programming for Xeon Phi on a Cray XC30 system. The university has 5 supercomputers (Camphor, Magnolia, Camellia, Laurel, and Cinnamon), with this talk covering programming for Camellia. The main challenges faced by Kyoto University were programming for: Inter-node = tough, intra-node = tougher, and intra-core = toughest (he described having to rewrite innermost kernels and redesign data structure for intra-core programming). He concluded that simple porting or large scale multi-threading may not be sufficient for good performance and SIMD-aware kernel recoding/redesign may be necessary.

Professor Hiroshi Nakashima’s slide on the Camellia supercomputer

Which brings me to possibly the hottest topic of the Developer Conference: the next Intel Xeon Phi processor (codename Knights Landing). Herbert Cornelius and Avinesh Sodani took the stage to give a few more details on the highly-anticipated processor arriving next year:

  • It will be available as a self-boot processor alleviating PCI Express bottlenecks, a self-boot processor + integrated fabric (Intel Omni-Path Architecture), or as an add-in card
  • Binary compatible with Intel Xeon processors (runs all legacy software, no recompiling)
  • The new core is Silvermont microarchitecture-based with many updates for HPC (offering 3x higher ST performance over current generation Intel Xeon Phi coprocessors)
  • Offers improved vector density (3+ teraflops (DP) peak per chip)
  • AVX 512 ISA (new 512-bit vector ISA with Masks)
  • Scatter/Gather engine (enabling hardware support for gather/scatter)
  • New memory technology MCDRAM + DDR (large high bandwidth memory – MCDRAM and huge bulk memory – DDR)
  • New on-die interconnect – MESH (high BW connection between cores and memory)

Next Intel Xeon Phi Processor (codename Knights Landing)

Another big priority for Intel is high fidelity visualization and measuring/modeling as an increasingly complex phenomenon. Jim Jeffers led a track on the subject and gave an overview presentation covering a couple of trends (increasing data size – no surprise there, and increasing shading complexity). He then touched on Intel’s high fidelity visualization solutions including software (Embree, the foundation for ray tracing in use by DreamWorks, Pixar, Autodesk, etc.) and efficient use of compute cluster nodes. Jim wrapped up by discussing an array of technical computing rendering tools developed by Intel and partners, which are all working to enable higher fidelity, higher capability, and better performance to move visualization work to the next level.

Jim Jeffers’s Visualization Tools Roadmap

These are just a few of the more than 20 sessions and topics (Lustre! Fabrics! Intel Math Kernel Library! Intel Xeon processor E5 v3!) at the HPC Developer Conference. The team is planning to post presentations to the Website in the next week, so check back for conference PDFs. If you attended the conference, please fill out your email survey – we want to hear from you on what worked and what didn’t. And if we missed you this year, drop us an email (contact info is at the bottom of the conference homepage) and we’ll make sure you get an invite in the future.