Like every other company that wants to gain an edge over the fast-moving competition, Intel wants to move even faster. Business velocity, as measured by the ability to bring more relevant products to market in less time, is a crucial aspect of succeeding in today’s accelerated marketplace. Market windows are becoming more critical; if Intel misses a market window (such as back-to-school or holiday shopping or a specific conference date), OEMs can’t use Intel’s products to make their own products, creating a ripple effect that slows the entire ecosystem.
Intel IT has been helping accelerate Intel’s time to market (TTM) for many years. However, this effort, which involves all of IT, really took off three to four years ago when we decided to take a new approach. Instead of different IT groups working on individual projects in pockets here and there, we took a step back to evaluate the challenges Intel was facing and how IT could make a difference. We realized that we needed to change how we interact with Intel’s product teams through a concerted, centralized effort. By doing so, we knew we could make a difference for some of Intel’s key projects.
We met with various product teams to discuss their biggest issues and then brainstormed with them about what IT might be able to do. Rather than waiting for product teams to come to us with specific requests, we said, “Tell us about your challenges, your struggles, and what’s holding you back,” and then used our IT expertise to develop solutions that solve those issues.
Where Does IT Innovation Fit into Product Design?
Before we illustrate some of the ways Intel IT has used IT innovation to speed product design and improve product quality at Intel, let’s briefly explore the traditional silicon design process. The figure below shows the three main phases: pre-silicon, manufacturing, and post-silicon. The basic process works like this: the design engineers come up with an idea and vet it through pre-silicon prototype development, emulation, and simulation. Eventually, the new product (a wafer) is manufactured, followed by post-silicon validation. If defects in the design are found during this phase, the cycle starts over with more testing, manufacturing, validation, and so on.
Of course, this general process of idea, test, manufacture, and validate isn’t limited to silicon design—it describes the production cycle for many types of products, from footwear to rocket ships. What we have done at Intel can serve as a model for other IT departments across a wide variety of industries to boost business velocity and product quality.
Each iteration, called a “step” or “stepping,” can take several months. Therefore, if we can reduce the number of steps, we can significantly speed TTM. Our System on a Chip (SoC) TTM program has set a goal of reducing TTM by approximately 40 percent. In 2016 we made significant progress toward that goal, and 2017 will see further improvements.
Shifting from a Serial to Parallel Process Reduces TTM
In one of our key efforts, we created a virtual infrastructure to support software design, allowing software and hardware design to move in parallel. This reduced Intel’s TTM and allowed testers to find defects earlier in the process.
Traditionally, the hardware design has been done first. Then, when the wafer came back from manufacturing, we developed the software (test scripts, firmware, OS optimization, and so on). This serial approach meant longer cycles and more steps as described earlier. In addition, software testing required vast amounts of compute power and was extremely expensive. Our solution? We created a virtual infrastructure to support design emulation and simulation so Intel’s engineers can perform hardware and software design simultaneously. The teams can access the virtual platform from anywhere in the world, at any time. We have consolidated our resources to provide a high level of scalability and quality of service. The virtual emulation/simulation environment has created significant business value and savings estimated at about one hundred million dollars.
Using Machine Learning to Increase Yield
When a silicon wafer returns from manufacturing, it is cut into hundreds of chips. Obviously, Intel wants the yield, or the percentage of chips that are free from defects, to be as high as possible. Each chip is tested to make sure it performs to the design specification. However, a negative test result could be a false positive; it could mean the test script was not executed properly. We use machine learning-based analytic capabilities to optimize testing processes and coverage and to predict whether a negative test result is due to an issue with the chip or with test execution. These new testing algorithms help Intel design teams achieve their goals in the most optimum time frame without missing corner cases. We also use machine learning to improve pre-silicon design quality, optimize design workflows, and reduce the number of design iterations. In 2016 our efforts resulted in a 30-percent stepping reduction on major intellectual property and SoC designs.
Learn More about the Business Value of IT Innovation
We continue to identify new, innovative ways for Intel IT to accelerate Intel’s product TTM. For more information about how Intel IT is creating business value at Intel, read our recently published 2016‒2017 Intel IT Annual Performance Report, “Accelerating the Pace of Business through IT Innovation.”