Today the Texas Advanced Computing Center (TACC), together with The University of Texas at Austin, announced that they will deploy a 10 Petaflop HPC Linux cluster called “Stampede.” When it is operational at the beginning of 2013, “Stampede” is expected to be among the most powerful computers in the world. Normally, we’d celebrate this important design, but for all of the Intel employees working on Intel® MIC Architecture for the past several years, this announcement has a very special meaning.
For Intel this is an exceptional announcement as those 10 Petaflops will be delivered entirely by Intel technology. “Stampede” will be based on future 8-core Intel® Xeon® processors E5 family (formerly known as Sandy Bridge-EP) that will deliver 2 petaflops of performance. But this is also the first announcement of a system that will include thousands of Intel® Many Integrated Core (Intel® MIC) architecture co-processors codenamed “Knights Corner.”, which will provide additional 8 Petaflops. In all, “Stampede’s” 10 petaflops performance will be achieved thanks to hundreds of thousands of Intel Xeon and Intel MIC cores – all based on Intel architecture.
These forthcoming Intel® Xeon processors E5 family, which are aimed at numerous market segments ranging from enterprise data centers, to cloud computing applications, to workstations and small businesses, are shipping to customers for revenue now. Intel is experiencing approximately 20x bigger demand for initial production units and 2x more design wins for this processors compared to the launch of the Intel® Xeon® processor 5500 series in 2009. We expect many high performance computing (HPC) and cloud customers to deploy their systems this year based on these new Intel Xeon processors with broad systems availability in early 2012.
“Knights Corner,” a co-processor aimed at highly parallel workloads, will be the first commercially available product featuring the Intel MIC architecture. “Knights Corner” is an innovative design that includes more than 50 cores and will be built using Intel’s leading edge 22nm 3D Tri-Gate transistor technology when in production.
It’s very important to understand why TACC choose to include Intel MIC architecture in Stampede. Since Intel MIC was announced more than a year ago at the International Supercomputer Conference (ISC) in Hamburg, more than 100 Intel MIC partners have been evaluating its potential. Earlier this year TACC joined other universities and research organizations around the world to build applications that take full advantage of the Intel MIC architecture. At this year’s ISC show in Hamburg, many of those MIC partners including Forschungszentrum Juelich, Leibniz Supercomputing Centre (LRZ), CERN and Korea Institute of Science and Technology Information (KISTI) shared their results, including how they were able to take advantage of the Intel MIC co-processor’s parallel processing capabilities while using well known IA instruction set. Using these widely available programming tools can help save time and money as it negates the need to learn any proprietary languages.
We believe the decision to build “Stampede” based on Intel Xeon processors E5 family and Intel MIC architecture based “Knights Corner” is a recognition of the advantages that standardized, high-level CPU programming models bring to developers of highly-parallel computing workloads. Being able to run the same code on both Intel Xeon processors and “Knights Corner” co-processors should allow developers to reuse their existing code and programming expertise which leads to greater productivity. Also, since Knights Corner is based on fully programmable Intel processors, it can run complex codes that are very difficult to program on more restrictive accelerator technologies.
TACC also announced that the current system is only the beginning as they plan to expand ”Stampede” in the future and increase the total system performance by more than 50 percent to 15 petaflops with the help of future generations of Intel products.
What does all of this mean for the future of HPC? Last week at the Intel Developer Forum, Kirk Skaugen, VP and GM of Intel’s Data Center and Connected Systems Group, talked about the huge growth that is expected in HPC in coming years. (For those who didn’t have a chance to attend IDF you can see video of Kirk’s presentation here -> part 1 & part 2). Our estimations show that by 2015, the world’s top 100 supercomputers will be powered by 2 million CPUs and by 2019 this number will reach 8 million CPUs. To give you a perspective, in 2010, Intel shipped about 8 million server processors in total.
This growth is fueled by the constant need for performance to solve some of the world’s biggest problems. Here’s one example: In 1997 the cost of sequencing a human genome was about a million dollars – mostly due to the scarcity of sufficient computing power. In 2009, the cost had dropped to $10,000. Due to continuing increases in compute performance, we believe that in a year or two the price can drop to $1,000. This relatively low cost might enable a patient to have his individual genome analyzed and an assessment made of his likelihood of contracting diseases. From there, preventative measures and treatments could be customized precisely for this one person. One of the keys to this “personalized medicine” is providing sufficient processing power to make the necessary calculations in as little time – and as cheaply – as possible.
Intel and HPC are a great match. Today, Intel processors power nearly 80 percent of the Top500 list of super-computers – which is great for our business. Overall, Technical Computing including HPC makes up about 30% of our data center business today. In response to the needs of technical computing developers and customers, Intel is committed to providing new technologies that will deliver even more performance to scientists to help fuel the next generation of scientific discovery. Again for those who were not at IDF, I recommend viewing a great video of a speech given by John Hengeveld, Director of HPC strategy at Intel. John discusses the future of supercomputing and why it’s critical to enable broader access to huge amounts of processing power.
This announcement of the first ever supercomputer combining the benefits of microprocessor and co-processors - without sacrificing the programming compatibility - is another step towards making access to HPC resources easier, more cost-effective, and more time-effective. This allows our scientists to focus on their own field of science and not the computer science.