Introducing Intel Agilex FPGAs for the New Era of Data-Centric Compute

Intel AgileX

Intel’s New FPGA Built on 10nm Technology Delivers Higher Performance while Using Less Power Compared with Prior-Generation FPGAs

A new era of data-centric computing from the edge to the network to the cloud is upon us, with a flood of data creating a critical need for flexibility and agility in the hardware, software, and solutions that process this data, wherever it is created, transported and stored.

The proliferation of data and the race to monetize that data are creating new opportunities for customer innovation across each of these markets, where field programmable gate arrays (FPGAs) have been so valued.

And that is why my team in Intel’s Programmable Solutions Group developed our new Intel® AgilexTM FPGA product family, our first fully Intel-optimized 10nm FPGA, announced today.

With the new Intel Agilex FPGA product family we are combining a number of unique elements which are made possible by Intel innovation and technology leadership, including:

Compute Express Link: Industry’s first FPGA to support Compute Express Link, a cache and memory coherent interconnect to future Intel® Xeon® Scalable processors.
2nd Generation HyperFlex: Up to 40 percent higher performance, or up to 40 percent lower total power compared with Intel® Stratix® 10 FPGAs.1
DSP Innovation: Only FPGA supporting hardened BFLOAT16 and FP16, providing up to 40 teraflops of digital signal processor (DSP) performance.2
Peripheral component interconnect express (PCIe) Gen 5: Higher bandwidth compared with PCIe Gen 4.
Transceiver Data Rates: Support up to 112 Gbps data rates.
Advanced memory support: DDR5, HBM, Intel® Optane™ DC persistent memory support.

While flexibility and scalability are common priorities for most applications, there are critical differences in the design challenges and requirements across edge, networking, and cloud customer markets:

• In the edge and embedded space, the priority is to deliver real-time actionable intelligence.
• In the networking space, the challenge is to accelerate virtualized network functions and deliver maximum data throughput at the component level.
• In the data center, the challenge is to manage, organize, and process the explosion of data and react to changing workload requirements. In each of these areas, FPGAs are accelerating diverse workloads and providing differentiated value to our customers.

While these trends and customer usage models are happening today, our customers also continue to need more performance, lower power, and higher levels of integration to provide the ultimate in agility and scalability in tomorrow’s designs.

More: Programmable Solutions Group News

Leveraging the powerful elements in our new Intel Agilex FPGAs enables Intel to deliver new levels of flexibility to our customers, and the agility to respond to specific markets needs with optimized products as never before.

And the impact of this technology innovation will be far-reaching. In the data center, customers will experience unparalleled flexibility and agility with better-than-ever acceleration of high-value workloads in applications spanning wireless and wired communications, industrial, high performance computing, video & image processing, data center, and more. With Intel Agilex FPGAs, customers will drive advances in health, medicine, science, technology and more, in addition to the core business advantages of making decisions faster using bigger data sets.

Armed with the capabilities provided by Intel Agilex FPGAs, Intel customers are well-positioned to deliver the next generation of transformative applications across the data-centric world.

I’m extremely excited about today’s Intel Agilex FPGA product family announcement for all of these reasons. I look forward to telling you about more innovations we’ll be unveiling in the weeks and months ahead, and more importantly, how our customers are using Intel technology to deliver some of the world’s most important innovations and advances.
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Results have been estimated or simulated using internal Intel analysis, architecture simulation, and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.

* Other names and brands may be claimed as the property of others.

For more complete information visit www.intel.com/benchmarks. Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate.

Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.

Further details on Intel Agilex performance, power, and software support numbers:

1 Up to 40 percent higher performance compared to Intel Stratix 10 FPGAs

Derived from benchmarking an example design suite comparing maximum clock speed (Fmax) achieved in Intel Stratix 10 devices with the Fmax achieved in Intel Agilex devices, using Intel Quartus Prime Software. On average, designs running in the fastest speed grade of Intel Agilex FPGAs achieve a 40 percent improvement in Fmax compared to the same designs running in the most popular speed grade of Stratix 10 devices (-2 speed grade), tested February 2019.

2 Up to 40 percent lower total power compared to Intel Stratix 10 FPGAs

Derived from benchmarking an example design suite comparing total power estimates of each design running in Intel Stratix 10 FPGAs compared to the total power consumed by the same design running in Intel Agilex FPGAs. Power estimates of Intel Stratix 10 FPGA designs are obtained from Intel Stratix 10 Early Power Estimator; power estimates for Intel Agilex FPGA designs are obtained using internal Intel analysis and architecture simulation and modeling, tested February 2019.

3 Up to 40 TFLOPs of DSP Performance (FP16 Configuration)

Each Intel Agilex DSP block can perform two FP16 floating-point operations (FLOPs) per clock cycle. Total FLOPs for FP16 configuration is derived by multiplying 2x the maximum number of DSP blocks to be offered in a single Intel Agilex FPGA by the maximum clock frequency that will be specified for that block.

Published on Categories Big Data and Analytics, Cloud Computing, Data Center NetworkingTags , , ,
Dan McNamara

About Dan McNamara

Daniel (Dan) McNamara is senior vice president and general manager of the Network and Custom Logic Group (NCLG) at Intel Corporation. In this role, McNamara leads a global organization that delivers maximum value for Intel’s customers across the Cloud, Enterprise, Network/5G, Embedded, and IOT markets. He is responsible for the group’s product lines and business strategies, focused on powering a broad portfolio of Intel products that includes Xeon, SoC, FPGA, eASIC, Full custom, software, IP, Systems and solutions. McNamara joined Intel in December 2015, upon close of Intel’s acquisition of Altera Corporation, where he served in various leadership roles, including vice president and general manager of Altera’s Embedded Division. McNamara has more than 25 years of experience in the semiconductor industry. Prior to Intel and Altera, McNamara served as director of Sales at StargGen Inc. and as co-founder and vice president of startup Semitech Solutions Inc. McNamara received his bachelor’s and master’s degrees, both in electrical engineering, from the Worcester Polytechnic Institute in Massachusetts.​