Industry-First Co-Packaged Optics Ethernet Switch Solution with Intel Silicon Photonics

My colleagues and I are proud of the flourishing high-volume business that Intel® Silicon Photonics has become since entering production in late 2016. Leading cloud service providers have now deployed more than three million of our 100G transceivers, and we continue to ship at a run rate of approximately two million units per year. Our products have achieved industry-leading quality and reliability benchmarks of less than 30 defective parts per million (DPPM), and we are ramping several new products this year, such as 200G FR4 and 400G DR4 pluggable transceivers.

But bringing optics onto the Intel silicon manufacturing platform has always been driven by a much bolder vision than just scaling pluggable transceivers: The vision of realizing optical I/O, where optics is connected directly to integrated circuits or networking silicon in the same multi-chip package. Such co-packaging would remove the constraints and inefficiencies of copper traces and eliminate the need for legacy pluggable interfaces that are located far away from the switch ASIC. As a result, co-packaged solutions will use less power, be less expensive, and easier to deploy than pluggable solutions.

We are now a significant step closer to making this vision a reality. We are announcing the successful demonstration of a new solution in which we have integrated optical I/O through 1.6Tbps Silicon Photonics engines in a 12.8 Tb/s P4-programmable Barefoot Tofino 2 Ethernet switch. This first-of-its-kind demonstration, passing DR4 standards compliant 400Gbps Ethernet traffic, puts Intel on track to enable the delivery of co-packaged optics products that leading data center providers will require in just a few years.

The Inevitability of Co-Packaged Optics

Driven by exponential growth in data and data opportunities in a multitude of industries, we are seeing demand for datacenter networking switch bandwidth double about every two years. Today, data centers at the leading edge operate switches with a bandwidth of 12.8 Tb/s. The industry is now looking ahead to 25.6 Tb/s switches in the next two years. 51.2 Tb/s switches may be fewer than four years, or two generations, away.

Pluggable modules like our 100 Gb/s Intel Silicon Photonics Optical Transceivers and the 200 Gb/s and 400 Gb/s solutions we are ramping throughout 2020 work great for current data centers, but the pluggable approach will not work forever. Pluggable solutions can’t achieve the density required for future generation switches, and customers desire greater power efficiency.

The answer for future data centers will be integrating photonics with the Ethernet switch directly in the same package, replacing pluggable interfaces with fiber connectors on the switch faceplate. This creates an opportunity to place the optical port in close proximity to the switch within the same package, reducing power and enabling greater switch bandwidth scalability.

This co-packaging of photonics with networking silicon is something that would be close to impossible with traditional optics. The long-term vision of greater scalability and reduced power consumption and size is a big reason why Intel invested in Silicon Photonics and why many customers are excited to be working with Intel.

Industry-First Optical I/O Integration with Ethernet Switch Silicon

Intel has developed a first-of-its-kind solution, demonstrating co-packaging of 1.6 Tb/s-bandwidth photonic engines with a 12.8 Tb/s P4-programmable Barefoot Networks Tofino 2 Ethernet switch. In this prototype demonstration, the 1.6 Tb/s photonic engines are realized as 4 ports of 400Gbase-DR4 interfaces. In future commercial products, the engine bandwidth will scale to 3.2 Tb/s per engine, co-packaged with 25.6Tb/s and 51.2Tb/s switches. The technologies and integration approach demonstrated in the prototype are all developed with high-volume manufacturing and flexible modularity in mind. As such, the solution can support a range of optical interfaces and requirements. The engines themselves are arrays of complete transceivers built around integrated silicon photonics chips with on-chip lasers and high-speed modulators and detectors and represent a next evolutionary step in Intel’s larger silicon photonics vision. The solution features a combination of co-packaged optical ports and copper ports supporting front-plate cages for optical modules or copper cables, highlighting the flexibility of the co-packaged switch.

With this demonstration of the feasibility of co-packaged optics, Intel is on-track to enable the delivery of co-packaged Intel Silicon Photonics solutions within two switch generations, in-line with predicted customer demand.

Leadership Technology for Silicon Photonics

Industry demand for solutions like this is in part demonstrated by the Co-Packaged Optics Collaboration, founded by Microsoft and Facebook with the goal of enabling the ecosystem to efficiently and economically co-package optics and switch silicon. Intel is at the forefront of the delivery of the Intel Silicon photonics technologies needed for co-packaged optics, and we are excited to work with the industry to make the future of optical I/O a reality.

For more detail on Intel’s industry-first co-packaged optics solution, please visit the Intel Newsroom. For more information on Intel Silicon Photonics solutions, please visit intel.com/siliconphotonics.

Notices & Disclaimers

Intel technologies may require enabled hardware, software or service activation.

No product or component can be absolutely secure. 

Your costs and results may vary. 

© Intel Corporation.  Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  Other names and brands may be claimed as the property of others.

Published on Categories Data CenterTags , , ,
Hong Hou

About Hong Hou

Dr. Hong Hou is the Corporate Vice President of the Data Platforms Group at Intel. Hong joined Intel in 2018 as Vice President of Data Center Group and General Manager of the Silicon Photonics Product Division. Prior to Intel, Hong has served as Executive Vice President and Chief Technical Officer for Fabrinet, Chief Operations Officer of AXT Inc., and as President, Chief Executive Officer and a member of the board of directors of Emcore Corporation. Early in his career, Hong conducted research at AT&T Bell Laboratories and Sandia National Laboratories on semiconductor materials and devices. Hong holds a Ph.D. in Electrical Engineering from the University of California at San Diego.