One of the eye-opening presentations at IDF 2010 was by David Fair and Jaya Jeyaseelan in the PCI Express Track entitled "Device Guidelines for PCI Express Technlogy Extensions." The evice extenstions referred tp power management opportunities for PCI Express devices. But not power management in the way you normally think of it.
It turns out that even low power devices can have an impact on power consumption of the computing platform much larger than the decive power itself. How? As Intel mobile power architect Jim Kardach explains it based on his experience with USB devices, “one crying baby can keep the whole household awake.”
A single low power device which constantly keeps the higher power consumption components on the platform from dropping into their lowest power states “keeps the whole house awake”. Each time a device “wakes up” this causes other devices to “wake up” as well. The net is the power consumption of the system far exceeds the the power the device itself. The “power savings opportunity” is shown in the picture below.
But there is a better way. Instead of jumping up immediately to change every diaper. David and Jaya discussed PCI Express extensions for cooperative power management and energy efficiency that allow software, through a Latency Tolerance Mechanism, to actively manage how quickly it needs to have system response. The cooperative element is that the tolerance can be adjusted depending on the level of device activity.
This provides an optimal power management solution becaue the platform enters lower power/longer latency states only when devices can tolerate it. Once the Latency Tolerance Register (LTR) is reprogrammed, the new LTR value is in effect no later than the value sent in the previous LTR. So when device activity is high, the LTR value is set to support it. When device activity drops to “idle” or “active idle” the LTR changes to a longer duratipon to enable greater energy savings.
A critical part of making this work is the management of device buffers. Without going into excess detail, a technique called “Optimized Buffer Flush/Fill” to classify transactions as critical (e.g. performance related) and deferrable (e.g. status notifications and debug stats) helps establish residency in deeper “C-states” for lower platform power.
While their presentation is on client systems, one can imagine how a crying baby might keep a data center awake. This capability could potentially benefit server and data center energy efficiency for many applications. And if you need any further proof, just remember how much energy it requires to take care of a crying baby...
If you’re a PCI device vendor or manufacturer, the call to action is to implement these cooperative power management features in your platforms. Collectively we need to work together to reduce system power consumption and collaboration between devices in the system is a must. For more help, work with your OEMs/ODMs to understand requirement and timeline and contact your Intel representative to get enabling tools and collateral.
To find out more, review the presentation on the Intel IDF 2010 website.
Download the PCI Express* 3.0 spec from the PCI-SIG Website (as of this writing the PCI Express Base 3.0 Draft Specification 0.9 is on the Review Zone ) for reference on LTR and OBFF. It is important that everyone starts architecting devices with a view towards using the Interconnect Bus extensions